3D THROUGH-SILICON VIA FILLING WITH ELECTROCHEMICAL NANOMATERIALS

被引:0
|
作者
Dubin, V. M. [1 ]
机构
[1] NANO3D SYST LLC, Portland, OR 97229 USA
关键词
BOTTOM-UP FILL; COPPER; PULSE; ELECTRODEPOSITION; STRENGTH; HOLES; ACID; ION;
D O I
暂无
中图分类号
O69 [应用化学];
学科分类号
081704 ;
摘要
This paper reviews electrochemical processes for the application in 3D through-silicon via fill technology. Electroplating, electroless plating and electrografting techniques are being investigated for barrier/seed and Cu superfill. Replacement of poor step coverage PVD barrier/seed with conformal electroless barrier/seed and low bottom up fill rate acceleration-based electroplating with superfill suppression-based electroplating will allow defect free-fill of high aspect ratio vias. Integration of electroless plating and electroplating will enable all-wet through-silicon via fill that exceed current fill techniques in scalability at lower process cost.
引用
下载
收藏
页码:331 / 339
页数:9
相关论文
共 50 条
  • [1] Through-Silicon Via Technology for 3D Applications
    Philipsen, Harold G. G.
    Luehn, Ole
    Civale, Yann
    Wang, Yu-Shuen
    Tezcan, Deniz Sabuncuoglu
    Ruythooren, Wouter
    PROCESSING, MATERIALS, AND INTEGRATION OF DAMASCENE AND 3D INTERCONNECTS, 2010, 25 (38): : 97 - 107
  • [2] Novel Through-Silicon Via Technologies for 3D System Integration
    Thadesar, Paragkumar A.
    Dembla, Ashish
    Brown, Devin
    Bakir, Muhannad S.
    PROCEEDINGS OF THE 2013 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2013,
  • [3] A Scalable Electrical Model for 3D IC with Through-Silicon Via
    Wu, Mei-Ling
    Chen, You-Yi
    JOURNAL OF THE CHINESE SOCIETY OF MECHANICAL ENGINEERS, 2016, 37 (06): : 635 - 645
  • [4] Overview and outlook of through-silicon via (TSV) and 3D integrations
    Lau, John H.
    MICROELECTRONICS INTERNATIONAL, 2011, 28 (02) : 8 - 22
  • [5] 3-D through-silicon via technology
    Vardaman, E. Jan
    Electronic Device Failure Analysis, 2008, 10 (04): : 30 - 32
  • [6] Copper-selective electrochemical filling of macropore arrays for through-silicon via applications
    Defforge, Thomas
    Billoue, Jerome
    Diatta, Marianne
    Tran-Van, Francois
    Gautier, Gael
    NANOSCALE RESEARCH LETTERS, 2012, 7
  • [7] Copper-selective electrochemical filling of macropore arrays for through-silicon via applications
    Thomas Defforge
    Jérôme Billoué
    Marianne Diatta
    François Tran-Van
    Gaël Gautier
    Nanoscale Research Letters, 7
  • [8] Development and Prospect of Coaxial Through-Silicon Via in 3D Integrated Circuits
    Junkai Ma
    Guangbao Shan
    Guoliang Li
    Zheng Liu
    Weihua Fan
    2023 24TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT, 2023,
  • [9] Dielectric Quality of 3D Capacitor Embedded in Through-Silicon Via (TSV)
    Lin, Ye
    Tan, Chuan Seng
    2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 1158 - 1163
  • [10] Thermal performance of 3D IC integration with Through-Silicon Via (TSV)
    Chien, H.-C. (Jack_Chien@itri.org.tw), 1600, IMAPS-International Microelectronics and Packaging Society (09):