A domain specific reconfigurable Viterbi fabric for system-on-chip applications

被引：0
|
作者：
Zhan, Cheng [1 ]
Arslan, Tughrul [1 ]
Khawam, Sami [1 ]
Lindsay, Iain [1 ]
机构：
[1] Univ Edinburgh, Sch Electron & Engn, Edinburgh EH9 3JL, Midlothian, Scotland
来源：
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel embedded dynamically reconfigurable fabric for implementing the Viterbi algorithm in a System-on-Chip device is presented in this paper. The proposed reconfigurable fabric can support Viterbi implementations for different standards, such as GSM, IS-95, CDMA and Wireless LAN. Our results illustrate that the proposed architecture has superior power consumption and throughput characteristics and it is demonstrated a 80% reduction in power consumption over generic field programmable gate array (FPGA) and 40 times improvement in throughput over digital signal processor (DSP), respectively. Thus, the reconfigurable system-on-chip platform based on this kind of domain specific reconfigurable fabrics is an efficient solution for the high-performance portable communication systems.
引用
收藏
页码：916 / 919
页数：4
相关论文
共 50 条
  • [31] Design verification and DFT for an embeddded reconfigurable low-power multiplier in system-on-chip applications
    Margala, M
    Chen, XL
    Xu, J
    Wang, HF
    14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2001, : 230 - 234
  • [32] System level modelling of reconfigurable FFT architecture for system-on-chip design
    Ahmadinia, Ali
    Ahmad, Balal
    Arslan, Tughrul
    NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS, PROCEEDINGS, 2007, : 169 - +
  • [33] Reconfigurable and Programmable System-on-Chip Hardware Platform for Real-time Ultrasonic Testing Applications
    Govindan, Pramod
    Wang, Boyang
    Wu, Pingping
    Palkov, Ivan
    Vasudevan, Vidya
    Saniie, Jafar
    2015 IEEE INTERNATIONAL ULTRASONICS SYMPOSIUM (IUS), 2015,
  • [34] Robust VLSI architecture for system-on-chip design and its implementation in viterbi decoder
    Hatakawa, Y
    Yoshizawa, S
    Miyanaga, Y
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 25 - 28
  • [35] A system-on-chip dynamically reconfigurable FPGA platform for matrix inversion
    Jianwen, Luo
    Chuen, Jong Ching
    2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2, 2007, : 465 - 468
  • [36] A reconfigurable system-on-chip architecture for medical imaging: Preliminary results
    Zhang, Hui
    Gu, Zi
    Xia, Mingxin
    Tang, Zhiwei
    Hu, Guangshu
    2005 27TH ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY, VOLS 1-7, 2005, : 1747 - 1749
  • [37] Dynamic hardware-software partitioning on reconfigurable system-on-chip
    Waldeck, P
    Bergmann, N
    3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2003, : 102 - 105
  • [38] Platform Independent GUI for Reconfigurable Ultrasonic System-on-Chip Hardware
    Boulet, Clementine
    Ricard, Eric Rovira
    Gilliland, Spenser
    Gonnot, Thomas
    Saniie, Jafar
    2014 IEEE INTERNATIONAL CONFERENCE ON ELECTRO/INFORMATION TECHNOLOGY (EIT), 2014, : 298 - 302
  • [39] SystemC-based design methodology for reconfigurable system-on-chip
    Qu, Y
    Tiensyrjä, K
    Soininen, JP
    DSD 2005: 8TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, PROCEEDINGS, 2005, : 364 - 371
  • [40] Hardware support for real-time reconfigurable system-on-chip
    Waldeck, PJ
    Bergmann, NW
    MICROELECTRONICS: DESIGN, TECHNOLOGY, AND PACKAGING, 2004, 5274 : 464 - 469
12345