A system-on-chip dynamically reconfigurable FPGA platform for matrix inversion

Dynamically and partially reconfigurable (DPR) FPGA computing platform offers flexibility on both the parallel computation as well as hardware reconfiguration at run-time Self-reconfiguration which allows the FPGA resource to be reconfigured partially by the on chip configuration controller offers even greater configuration bandwidth. We design and put together a set of functional modules and compose a FPGA-based system-on-chip (SoC) DPR platform for hardware acceleration. Matrix inversion is used as an example to illustrate the design and operation of such a reconfiguration system. The proposed platform consists of a configurable module, in this case, a scalable CORDIC based QR factorization core designed for matrix inversion and a fixed module to support the dynamic partial reconfiguration. This paper describes the architecture and the components of the proposed DPR platform.