Using an SCR as ESD protection without latch-up danger

被引：38
|
作者：
Notermans, G
Kuper, F
Luchies, JM
机构：
[1] Philips Semiconductors, MOS4, FB-2, 6534 AE Nijmegen
来源：
MICROELECTRONICS AND RELIABILITY | 1997年 / 37卷 / 10-11期
关键词：
D O I：
10.1016/S0026-2714(97)00086-3
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A properly designed Low-Voltage Triggering SCR has a four times better ESD performance than a conventional grounded-gate NMOST of the same width. But it does present a latch-up risk due to its low holding voltage. The holding voltage can be increased by using a larger anode-to-cathode spacing, but at very large spacings the ESD performance decreases. It is shown that a window in SCR anode-to-cathode spacing exists, for which the holding voltage is sufficiently large, while the excellent ESD protection properties are preserved. (C) 1997 Elsevier Science Ltd.
引用
收藏
页码：1457 / 1460
页数：4
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