A Charge Pump PLL with Fast-locking Strategies Embedded in FPGA in 65nm CMOS Technology

Phase-locked loops (PLL) have been widely utilized in FPGA as an important module for clock management. In this paper, a charge pump PLL with fast-locking strategies embedded in 65nm FPGA is proposed. Firstly, a configurable prestart circuit is utilized to initialize the operation state of PLL. Secondly, a bandwidth switch strategy is proposed to manage the contradiction between locking speed and noise performance. Thirdly, the PLL incorporates a VCO with dual control voltages to accelerate the adjustment of oscillation frequency. Simulation results demonstrate that the proposed fast-locking PLL can lock in 2.20 mu s with a reference clock of 50MHz and an output clock of 1GHz, acquiring an 81.5% reduction in locking time compared to traditional PLL.