Design and Analysis of Charge Pump for PLL at 90nm CMOS Technology

被引：0
|
作者：
Chandra, Ravi [1 ]
Anurag [2 ]
机构：
[1] C DAC, VLSI Design, Mohali, India
[2] C DAC, ACSD, Mohali, India
来源：
2015 2ND INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN ENGINEERING & COMPUTATIONAL SCIENCES (RAECS) | 2015年
关键词：
Charge Pump (CP); Phase Lock Loop (PLL); ADE(Analog Digital Environment); PVT(Process; Voltage and Temperature) variation; Monte Carlo Simulation; Operational Amplifier; Current Mirror Circuit etc;
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
The aim of this research is to design a charge pump to improve current matching, wide range of output voltage, fast switching operation and reduce charge sharing in transistor. The design of charge pump is proposed and simulated in cadence virtuoso ADE and ADXL tools at 90nm CMOS technology. Current mismatching is analysed with Monte Carlo simulation and output variation is calculated on PVT. The designed charge pump achieves wide output voltage swing 0.5 similar to 1V, improve current mismatching approximate 0.5% and power dissipation of 320 mu W.
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页数：5
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