A Charge Pump PLL with Fast-locking Strategies Embedded in FPGA in 65nm CMOS Technology

被引：1
|
作者：
Yang, Mingqian [1 ]
Chen, Lei [1 ]
Li, Xuewu [1 ]
Zhang, Yanlong [1 ]
机构：
[1] Beijing Microelect Technol Inst, Beijing, Peoples R China
来源：
PROCEEDINGS OF 2017 2ND INTERNATIONAL CONFERENCE ON COMMUNICATION AND INFORMATION SYSTEMS (ICCIS 2017) | 2015年
关键词：
Charge pump PLL; Fast-locking; FPGA;
D O I：
10.1145/3158233.3159315
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Phase-locked loops (PLL) have been widely utilized in FPGA as an important module for clock management. In this paper, a charge pump PLL with fast-locking strategies embedded in 65nm FPGA is proposed. Firstly, a configurable prestart circuit is utilized to initialize the operation state of PLL. Secondly, a bandwidth switch strategy is proposed to manage the contradiction between locking speed and noise performance. Thirdly, the PLL incorporates a VCO with dual control voltages to accelerate the adjustment of oscillation frequency. Simulation results demonstrate that the proposed fast-locking PLL can lock in 2.20 mu s with a reference clock of 50MHz and an output clock of 1GHz, acquiring an 81.5% reduction in locking time compared to traditional PLL.
引用
收藏
页码：131 / 135
页数：5
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