Low power dual-edge triggered flip-flop structure in quantum dot cellular automata

被引：40
|
作者：
Yang, X. [1 ]
Cai, L. [1 ]
Zhao, X. [1 ]
机构：
[1] AF Engn Univ, Coll Sci, Xian 710051, Peoples R China
来源：
ELECTRONICS LETTERS | 2010年 / 46卷 / 12期
关键词：
Flip flop circuits;
D O I：
10.1049/el.2010.1090
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Artificial molecule quantum dot cells are a promising currentless nanotechnology, which can be used for realising fully digital circuits and systems. A dual-edge triggered module and flip-flop sequential circuit are proposed using quantum dot cellular automata (QCA) cells by arranging special clock zones subtly and serially. A D flip-flip case is given to show how a low power dual-edge triggered flip-flop can be realised using quantum dot cell arrays. The proposed structure is promising in building future nanoscale ultra low power information processing systems and may inspire higher clock speed applications in QCA.
引用
收藏
页码：825 / U35
页数：2
相关论文
共 50 条
  • [31] Design of low-power double edge-triggered flip-flop circuit
    Chien-Cheng, Yu
    ICIEA 2007: 2ND IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS, VOLS 1-4, PROCEEDINGS, 2007, : 2054 - 2057
  • [32] DOUBLE-EDGE TRIGGERED FLIP-FLOP
    GHALLEY, JS
    ELECTRONIC ENGINEERING, 1985, 57 (705): : 16 - 16
  • [33] A Novel Design of Low-Power Double Edge-Triggered Flip-Flop
    Yu, Chien-Cheng
    Chen, Kuan-Ting
    Wun, Jhong-yu
    PROCEEDINGS OF THE 2ND INTERNATIONAL CONFERENCE ON INTELLIGENT TECHNOLOGIES AND ENGINEERING SYSTEMS (ICITES2013), 2014, 293 : 947 - 955
  • [34] Low power double edge-triggered flip-flop using one latch
    Strollo, AGM
    Napoli, E
    Cimino, C
    ELECTRONICS LETTERS, 1999, 35 (03) : 187 - 188
  • [35] DOUBLE-EDGE TRIGGERED FLIP-FLOP
    ALDWORTH, CP
    ELECTRONIC ENGINEERING, 1985, 57 (703): : 36 - 36
  • [36] A Novel Modified Low Power Pulse Triggered Flip-Flop
    Samal, Lopamudra
    Sahoo, Sauvagya Ranjan
    Samal, Chiranjibi
    2017 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, COMMUNICATION, COMPUTER, AND OPTIMIZATION TECHNIQUES (ICEECCOT), 2017, : 482 - 488
  • [37] Implementation of the clock edge controllable dual edge-triggered D flip-flop using the cellular neural network
    Liu, Y.-Y. (yyliu@njfu.edu.cn), 1600, Beijing University of Posts and Telecommunications (36):
  • [38] Low-power clock branch sharing double-edge triggered flip-flop
    Zhao, Peiyi
    McNeely, Jason
    Golconda, Pradeep
    Bayoumi, Magdy A.
    Barcenas, Robert A.
    Kuang, Weidong
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (03) : 338 - 345
  • [39] A novel CMOS double-edge triggered flip-flop for low-power applications
    Sung, YY
    Chang, RC
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 665 - 668
  • [40] Applying inherent capabilities of quantum-dot cellular automata to design: D flip-flop case study
    Shamsabadi, Abbas Shahini
    Ghahfarokhi, Behrouz Shahgholi
    Zamanifar, Kamran
    Movahedinia, Naser
    JOURNAL OF SYSTEMS ARCHITECTURE, 2009, 55 (03) : 180 - 187
12345