Crosstalk Computing-Based Gate-Level Reconfigurable Circuits

被引:2
|
作者
Macha, Naveen Kumar [1 ]
Repalle, Bhavana Tejaswini [1 ]
Iqbal, Md Arif [2 ]
Rahman, Mostafizur [2 ]
机构
[1] NVIDIA, Santa Clara, CA 95051 USA
[2] Univ Missouri, Dept Comp Sci Elect Engn, Kansas City, MO 64110 USA
关键词
Logic gates; Couplings; Transistors; Metals; Capacitance; Integrated circuit modeling; Crosstalk; Crosstalk (CT) circuits; crosstalk computing; polymorphic circuits; reconfigurable circuits; DESIGN;
D O I
10.1109/TVLSI.2022.3173344
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The functionality of polymorphic circuits can be altered using a control variable. Owing to the multifunctional embodiment in polymorphic circuits, they are helpful to reconfigure circuit behavior from the gate level to the system level, either on the fly or off-line. The polymorphic circuit approaches available in the literature are either based on custom nonlinear circuit designs or special emerging devices, such as ambipolar FET and configurable magnetic devices. While some of these approaches are inefficient in performance, the other approaches involve exotic devices. We have proposed a novel polymorphic circuit design approach based on crosstalk (CT) computing, where we leverage deterministic signal interference between nanometal lines for logic computation and reconfiguration. In this article, we elaborate upon the polymorphic circuit design in CT computing through mathematical formulation, which conveys the rationale to generalize and achieve a wide variety of polymorphic circuits, and then demonstrate a comprehensive list of polymorphic circuit designs. In addition, all circuits are characterized and benchmarked against CMOS circuit implementations to gauge the benefits. Finally, we compare the CT polymorphic circuit approach with other approaches in the literature and highlight its unique features and limitations. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to CT computing, which leads to benefits in the circuit power, performance, and area (PPA). Our circuit designs, simulation, and PPA characterization results show that the polymorphic CT circuits provide 3x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in speed for polymorphic logic circuits. In the best-case, the transistor count reduction is 5x.
引用
收藏
页码:1073 / 1083
页数:11
相关论文
共 50 条
  • [41] Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level
    Xu, Siyuan
    Schafer, Benjamin Carrion
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (11) : 3077 - 3088
  • [42] Topological constraints of gate-level circuits obtained through standard cell recognition (SCR)
    Hsia, L. A.
    Vernizzi, G.
    Lanzerotti, M. Y.
    Langley, D.
    Seery, M. K.
    Orlando, L.
    PROCEEDINGS OF THE 2015 IEEE NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE (NAECON), 2015, : 165 - 175
  • [43] Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines
    Albano, D.
    Lanuzza, M.
    Taco, R.
    Crupi, F.
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2015, 43 (11) : 1523 - 1540
  • [44] Guided Gate-level ATPG for Sequential Circuits using a High-level Test Generation Approach
    Alizadeh, Bijan
    Fujita, Masahiro
    2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 420 - 425
  • [45] Using gate-level side channel parameters for formally analyzing vulnerabilities in integrated circuits
    Abbassi, Imran Hafeez
    Khalid, Faiq
    Hasan, Osman
    Kamboh, Awais Mehmood
    SCIENCE OF COMPUTER PROGRAMMING, 2019, 171 : 42 - 66
  • [46] A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits
    Elgharbawy, W
    Golconda, P
    Kumar, A
    Bayoumi, M
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4697 - 4700
  • [47] Clock period minimization of semi-synchronous circuits by gate-level delay insertion
    Yoda, T
    Takahashi, A
    Kajitani, Y
    PROCEEDINGS OF ASP-DAC '99: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1999, 1999, : 125 - 128
  • [48] Clock period minimization of semi-synchronous circuits by gate-level delay insertion
    Yoda, T
    Takahashi, A
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1999, E82A (11) : 2383 - 2389
  • [49] SIFLAP-G - A METHOD OF DIAGNOSING GATE-LEVEL FAULTS IN COMBINATIONAL-CIRCUITS
    YAMAZAKI, K
    YAMADA, T
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1993, E76D (07) : 826 - 831
  • [50] Reliability Optimization of Reconfigurable Computing-Based Fault-Tolerant System
    Zhou, Mi
    Shang, Lihong
    Hu, Yu
    HPCC: 2009 11TH IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2009, : 369 - +