Systematic evaluation of SOI Buried Oxide Reliability for Partially Depleted and Fully Depleted applications

被引:0
|
作者
Schwarzenbach, W. [1 ]
Malaquin, C. [1 ]
Allibert, F. [1 ]
Besnard, G. [1 ]
Nguyen, B. -Y. [1 ]
机构
[1] SOITEC, Parc Technol Fontaines, F-38190 Bernin, France
关键词
Fully Depleted SOI; Partially Depleted SOI; BOX Breakdown; Leakage current;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
SOI Buried Oxide (BOX) electrical quality is assessed through Charge to Breakdown, Breakdown Voltage, low field leakage, BOX fixed charge density and BOX/ Si interface trap density measurements. Breakdown electrical field higher than 10 MV. cm(-1) and 10 years lifetime at operating voltages in excess of 16V are reported on thin BOX layers.
引用
收藏
页数:3
相关论文
共 50 条
  • [41] A Unified Analytical One-Dimensional Surface Potential Model for Partially Depleted (PD) and Fully Depleted (FD) SOI MOSFETs
    Pandey, Rahul
    Dutta, Aloke K.
    JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2011, 11 (04) : 262 - 271
  • [42] Comparison of Three Dimensional Partially and Fully Depleted SOI MOSFET Characteristics Using Mathcad
    Goel, Neha
    Pandey, Manoj Kumar
    JOURNAL OF NANO- AND ELECTRONIC PHYSICS, 2016, 8 (01)
  • [43] A continuous compact MOSFET model for fully- and partially-depleted SOI devices
    Sleight, JW
    Rios, R
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (04) : 821 - 825
  • [44] Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs
    Rafi, J. M.
    Simoen, E.
    Mercha, A.
    Hayama, K.
    Campabadal, F.
    Ohyama, H.
    Claeys, C.
    MICROELECTRONIC ENGINEERING, 2007, 84 (9-10) : 2081 - 2084
  • [45] Electrical measurement of silicon film and oxide thicknesses in partially depleted SOI technologies
    Tenbroek, BM
    RedmanWhite, W
    Lee, MSL
    Uren, MJ
    SOLID-STATE ELECTRONICS, 1996, 39 (07) : 1011 - 1014
  • [46] Fully depleted SOI-CMOS technology for high temperature IC applications
    Universite Catholique de Louvain, Louvain-la-Neuve, Belgium
    Mater Sci Eng B Solid State Adv Technol, 1-3 (1-7):
  • [47] Effects of techniques of implanting nitrogen into buried oxide on the characteristics of partially depleted SOIPMOSFET
    Zheng, ZS
    Liu, ZL
    Zhang, GQ
    Li, N
    Fan, K
    Zhang, EX
    Yi, WB
    Chen, M
    Wang, X
    CHINESE PHYSICS LETTERS, 2005, 22 (03) : 654 - 656
  • [48] Fully depleted SOI-CMOS technology for high temperature IC applications
    Gentinne, B
    Eggermont, JP
    Flandre, D
    Colinge, JP
    MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY, 1997, 46 (1-3): : 1 - 7
  • [49] Fully depleted CMOS/SOI device design guidelines for low power applications
    Banna, SR
    Chan, PCH
    Chan, MS
    Fung, SKH
    Ko, PK
    1997 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, PROCEEDINGS, 1997, : 301 - 306
  • [50] Fully depleted SOI CMOS logic gates for low-voltage applications
    Masal'skii N.V.
    Russian Microelectronics, 2008, 37 (06) : 410 - 417