Systematic evaluation of SOI Buried Oxide Reliability for Partially Depleted and Fully Depleted applications

被引：0

作者：

Schwarzenbach, W. ^{[1
]}

Malaquin, C. ^{[1
]}

Allibert, F. ^{[1
]}

Besnard, G. ^{[1
]}

Nguyen, B. -Y. ^{[1
]}

机构：

[1] SOITEC, Parc Technol Fontaines, F-38190 Bernin, France

来源：

2015 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2015年

关键词：

Fully Depleted SOI; Partially Depleted SOI; BOX Breakdown; Leakage current;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

SOI Buried Oxide (BOX) electrical quality is assessed through Charge to Breakdown, Breakdown Voltage, low field leakage, BOX fixed charge density and BOX/ Si interface trap density measurements. Breakdown electrical field higher than 10 MV. cm(-1) and 10 years lifetime at operating voltages in excess of 16V are reported on thin BOX layers.

引用

页数：3

共 50 条

[21] A novel methodology for reliability studies in fully-depleted SOI MOSFETs
Banna, SR
Chan, PCH
Wong, SS
Fung, SKH
Ko, PK
1997 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 35TH ANNUAL, 1997, : 296 - 299
[22] Fully depleted SOI (FDSOI) technology
Kangguo CHENG
Ali KHAKIFIROOZ
ScienceChina(InformationSciences), 2016, 59 (06) : 20 - 34
[23] Substrate effect on radiation-induced charge trapping in buried oxide for partially-depleted SOI NMOSFET
Zhu H.
Bi D.
Xie X.
Hu Z.
Zhang Z.
Zou S.
Bi, Dawei (davidb@mail.sim.ac.cn), 1600, Institute of Electronics Information Communication Engineers (17) : 1 - 6
[24] Substrate effect on radiation-induced charge trapping in buried oxide for partially-depleted SOI NMOSFET
Zhu, Huilong
Bi, Dawei
Xie, Xin
Hu, Zhiyuan
Zhang, Zhengxuan
Zou, Shichang
IEICE ELECTRONICS EXPRESS, 2020, 17 (07):
[25] A simulation study on thin SOI bipolar transistors with fully or partially depleted collector
Ouyang, QQ
Cai, J
Ning, T
Oldiges, P
Johnson, JB
PROCEEDINGS OF THE 2002 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2002, : 28 - 31
[26] Heterojunction fully depleted SOI-TFET with oxide/source overlap
Chander, Sweta
Bhowmick, B.
Baishya, S.
SUPERLATTICES AND MICROSTRUCTURES, 2015, 86 : 43 - 50
[27] Partially depleted CMOS SOI technology for low power RF applications
Tinella, C.
Gianesello, F.
Gloria, D.
Raynaud, C.
Delatte, P.
Engelstein, A.
Fournier, J. M.
Benech, Ph.
Jomaah, J.
GAAS 2005: 13TH EUROPEAN GALLIUM ARSENIDE AND OTHER COMPOUND SEMICONDUCTORS APPLICATION SYMPOSIUM, CONFERENCE PROCEEDINGS, 2005, : 101 - 104
[28] Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability
Schwarzenbach, Walter
Nguyen, Bich-Yen
Allibert, Frederic
Girard, Christophe
Maleville, Christophe
SOLID-STATE ELECTRONICS, 2016, 117 : 2 - 9
[29] FULLY-DEPLETED SUBMICRON SOI FOR RADIATION-HARDENED APPLICATIONS
BRADY, FT
SCOTT, T
BROWN, R
DAMATO, J
HADDAD, NF
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1994, 41 (06) : 2304 - 2309
[30] Fully depleted SOI process and device technology for digital and RF applications
Ichikawa, F
Nagatomo, Y
Katakura, Y
Itoh, M
Itoh, S
Matsuhashi, H
Ichimori, T
Hirashita, N
Baba, S
SOLID-STATE ELECTRONICS, 2004, 48 (06) : 999 - 1006

← 1 2 3 4 5 →