VLSI Implementation of an improved multiplier for FFT Computation in Biomedical Applications

被引：6

作者：

Ajay, Arathi ^{[1
]}

Lourde, R. Mary ^{[1
]}

机构：

[1] BITS Pilani, Dept Elect & Elect Engn, Dubai Campus, Dubai, U Arab Emirates

来源：

2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI | 2015年

关键词：

FFT; Multiplier; EEG;

D O I：

10.1109/ISVLSI.2015.104

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Discrete Fourier Transform (DFT) is a fundamental Digital Signal Processing domain transformation technique used in many applications for frequency analysis and frequency domain processing. Fast Fourier Transform (FFT) is used for signal processing applications. It consists of addition and multiplication operations, whose speed improvement will enhance the accuracy and performance of FFT computation for any application. It is an algorithm to compute Discrete Fourier Transform (DFT) and its inverse. DFT is obtained by decomposing a sequence of values into components of different frequencies. FFT can compute DFT in O(N log N) operations unlike DFT computation that takes O(N2) arithmetic operations. This reduces computation time by several orders of magnitude and the improvement is roughly proportional to N / log N. Present day Research focus is on performance improvement in computation of FFT specific to field of application. Many performance improvement studies are in progress to implement efficient FFT computation through better performing multipliers and adders. Electroencephalographic (EEG) signals are invariably used for clinical diagnosis and conventional cognitive neuroscience. This work intends to contribute to a faster method of computation of FFT for analysis of EEG signals to classify Autistic data.

引用

页码：68 / 73

页数：6

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