Implementation of 32-bit RISC processors without interlocked Pipelining on Artix-7 FPGA Board

被引：0
|
作者：
Rohit, J. [1 ]
Raghavendra, M. [1 ]
机构：
[1] PESIT BSC, Dept ECE, Bangalore, Karnataka, India
来源：
2017 2ND INTERNATIONAL CONFERENCE ON CIRCUITS, CONTROLS, AND COMMUNICATIONS (CCUBE) | 2017年
关键词：
RISC; clock; 5-Stage Pipeline; FPGA;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
RISC processors have wide range of applications depending on speed and power consumption. Here a design of low power RISC processor is proposed using forwarding and stalling process. Using suitable clocking methodology speed can also be enhanced. A design of 5 stage pipelining architecture with hazard and forwarding unit for pipeline control is presented. Fetch, Decode, Execute, Memory and Write back are the 5 stages. A single edge trigger clock is used for intermediate stages. The RISC processor is designed based on MIPS instruction set. A non-interlocked pipelining technique is used. Power reduction of up to 09W was achieved using above mentioned techniques. The design is implemented on Artix-7 FPGA using Xilinx Vivado.
引用
收藏
页码：105 / 108
页数：4
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