共 50 条
- [21] The PIXBAR OPC for Contact-Hole Pattern in sub-70-nm Generation DESIGN FOR MANUFACTURABILITY THROUGH DESIGN-PROCESS INTEGRATION III, 2009, 7275
- [22] Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits 2018 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFT), 2018,
- [24] Implementation of sub-150 nm contact hole pattern by resist flow process JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1998, 37 (12B): : 6863 - 6868
- [26] RET application in 45nm node and 32nm node contact hole dry ArF lithography process development OPTICAL MICROLITHOGRAPHY XX, PTS 1-3, 2007, 6520
- [27] Practical LEEPL masks for sub-65-nm node 24TH ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PT 1 AND 2, 2004, 5567 : 1268 - 1277
- [28] Double exposure for the contact layer of the 65-nm node Advances in Resist Technology and Processing XXII, Pt 1 and 2, 2005, 5753 : 171 - 180
- [29] Optimizing manufacturability for the 65nm process node DESIGN AND PROCESS INTEGRATION FOR MICROELECTRONIC MANUFACTURING, 2003, : 326 - 333
- [30] Ultra shallow junction formation using plasma doping and laser annealing for sub-65 nm technology nodes JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2006, 45 (4B): : 2961 - 2964