Optimizing manufacturability for the 65nm process node

The 65nm technology node will require a more detailed assessment of the tradeoffs between performance, manufacturability and cost than any previous generation of technology. Circuits fabricated at the 65nm technology node need to use Strong Phase shifting techniques such as Full-Phase and Model based OPC in order to guarantee printability of critical layers, such as the poly layer. We present a methodology whereby layouts are generated based on a preliminary set of design rules for 65nm and the process latitude determined using image simulation software. Mask costs were also estimated based on figure counts of the required masks. Tradeoffs between mask costs, manufacturability and density were made by small changes to the design rules. The simultaneous use of tools that integrate the design creation process with mask generation allows far better optimization than current methodology where physical design is separated from the downstream data preparation and processing.