Optimizing ALD WN process for 65nm node CMOS contact application

被引：0

作者：

Chen, Y. -C. ^{[1
]}

Hung, T. -Y. ^{[1
]}

Chang, Y. -L. ^{[1
]}

Shieh, K. ^{[1
]}

Hsu, C. -L. ^{[1
]}

Huang, C. ^{[1
]}

Yan, W. H. ^{[2
]}

Ashtiani, K. ^{[2
]}

Pisharoty, D. ^{[2
]}

Lei, W. ^{[2
]}

Chang, S. ^{[2
]}

Huang, F. ^{[2
]}

Collins, J. ^{[2
]}

Tzou, S. F. ^{[1
]}

机构：

[1] United Microelect Corp, 18,Nanke 2nd Rd Tainan Sci Pk, Tainan 741, Taiwan

[2] Novellus Systs Inc, San Jose, CA 95134 USA

来源：

PROCEEDINGS OF THE IEEE 2007 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE | 2007年

关键词：

D O I：

暂无

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

ALD tungsten nitride (WN) becomes attractive for CMOS contact liner/barrier application because of its highly conductive and conformal film properties. Due to the distinct differences in its process nature from the traditional. PVD processes, a full optimization from film properties to process integration is necessary for the 65nm CMOS device fabrication. This paper highlights the issues and shows the approaches to address these issues in implementing the ALD WN process for the CMOS contact application.

引用

页码：105 / +

页数：2

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