Wafer flatness requirements for 45nm node (65nm hp) lithography process

被引：1
|
作者：
Okazaki, Motoya [1 ]
Ciari, R. [1 ]
James, L. [1 ]
Meng, B. [1 ]
Thompson, M. [1 ]
Dai, H. [1 ]
Xu, X. [1 ]
Liu, I. [1 ]
Dorflinger, D. [1 ]
Yung, B. [1 ]
Ngai, C. [1 ]
机构：
[1] Appl Mat Inc, Santa Clara, CA 95052 USA
来源：
2008 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE | 2008年
关键词：
wafer; flatness; SFQR; lithography; defocus; defect;
D O I：
10.1109/ASMC.2008.4529070
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：356 / 358
页数：3
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