Design of Ultra Low Power Asynchronous Domino Logic Pipeline Using Critical Data Path

被引：0

作者：

Nirmala, K. ^{[1
]}

Babu, P. Prasanth ^{[1
]}

Prasanth, K. ^{[1
]}

Kumar, D. Maruthi ^{[1
]}

机构：

[1] Srinivasa Ramanujan Inst Technol, Elect & Commun Engn, Ananthapuramu 515701, AP, India

来源：

EMERGING TRENDS IN ELECTRICAL, COMMUNICATIONS AND INFORMATION TECHNOLOGIES | 2017年 / 394卷

关键词：

D O I：

10.1007/978-981-10-1540-3_25

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents Design of ultra low-power asynchronous domino logic pipeline method, which targets to introduce design of latch-free pipe-line targeting to latch-free pipeline. To construct data paths, both dual rail and single rail domino gates are used. Dual-rail domino gates are mainly used to construct critical data paths. Hence the handshake signals are reduced greatly, using critical data path. This pipeline offers low power consumption and high throughput. A 16 x 16 array style multiplier is used for evaluating the proposed pipeline method. Asynchronous static pipeline method is compared with the proposed pipeline method, it saves up to 83.0 and 16.4 % of power.

引用

页码：237 / 247

页数：11

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