A Novel Method to Predict Die Shift During Compression Molding in Embedded Wafer Level Package

被引:0
|
作者
Khong, Chee Houe [1 ]
Kumar, Aditya [1 ]
Zhang, Xiaowu [1 ]
Sharma, Gaurav [1 ]
Vempati, Srinivasa Rao [1 ]
Vaidyanathan, Kripesh [1 ]
Lau, John Hon-Shing [1 ]
Kwong, Dim-Lee [1 ]
机构
[1] ASTAR, Inst Microelect, Singapore 117685, Singapore
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The increased functionality of cellular phones and handheld devices requires system level integration. Thus there is a strong demand in cell phone maker to move to embedded micro wafer level packaging (EMWLP). But the major problem encountered is die shift during compression molding. This paper presents a novel method to predict the die shift during wafer level molding process. A series of parametric studies are performed by changing the die thickness, die pitch distance and top mold chaste compression velocity. The effect of thinning down the chip thickness affects the pressure difference and local shear rate on the chip surfaces. The rate of change of epoxy mold compound fluid pressure across the die top surfaces is not constant. The local shear rate is increasing linearly from the centre of the wafer to the outermost die. From the parametric studies, the die shift is inversely proportional to the die thickness for wafer level molding. Such a phenomenon will reduce the lithography alignment error in the next process. This paper also shows that by reducing die pitch distance of a 5 x 5 mm(2), 500 mu m thick chip, the die shift decreases by a factor of 12%. In addition, the top mold chaste compression velocity contributes to the die shift by as much as 28% when the velocity is reduced by 50% from 100 mu m/sec to 50 mu m/sec Finally it is observed from experiment result that the die shift is not constant in all directions.
引用
收藏
页码:535 / 541
页数:7
相关论文
共 50 条
  • [21] Heat Dissipation Capability of a Package-on-Package Embedded Wafer-Level Package
    Han, Yong
    Lau, Boon Long
    Jung, Boo Yang
    Zhang, Xiaowu
    [J]. IEEE DESIGN & TEST, 2015, 32 (04) : 32 - 39
  • [22] Development of Package-on-Package Using Embedded Wafer-Level Package Approach
    Chong, Ser Choong
    Wee, David Ho Soon
    Rao, Vempati Srinivasa
    Vasarla, Nagendra Sekhar
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (10): : 1654 - 1662
  • [23] Development of Advanced Fan-out Wafer Level Package (embedded Wafer Level BGA)
    Jin, Yonggang
    Teysseyre, Jerome
    Liu, Anandan Ramasy Yun
    Goh, George
    Yoon, S. W.
    [J]. 2012 35TH IEEE/CPMT INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM (IEMT), 2012,
  • [24] Package-Level Thermal Management of a 3D Embedded Wafer Level Package
    Han, Yong
    Zheng, Boyu
    Choong, Chong Ser
    Jung, Boo Yang
    Zhang, Xiaowu
    [J]. PROCEEDINGS OF THE 2013 IEEE 15TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2013), 2013, : 78 - 82
  • [25] Wafer level encapsulation - A transfer molding approach to system in package generation
    Braun, T
    Becker, KF
    Koch, M
    Bader, V
    Oestermann, U
    Manessis, D
    Aschenbrenner, R
    Reichl, H
    [J]. PROCEEDINGS OF THE 4TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2002), 2002, : 235 - 244
  • [26] Three Dimensional Compression Molding Simulation for Wafer Level Packaging
    Hsu, Chih-Chung
    Weng, Wen-Hsin
    Chiu, Hsien-Sen
    Chang, Rong-Yeu
    [J]. 2013 8TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2013, : 234 - 237
  • [27] Novel Integrated Package-on-Package for Wafer Level and Panel Level Production
    Koh, Wei
    [J]. 2020 21ST INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2020,
  • [28] Development of Advanced Fan-out Wafer Level Package (embedded Wafer Level BGA) Packaging
    Jin, Yonggang
    Teysseyre, Jerome
    Baraton, Xavier
    Yoon, S. W.
    Lin, Yaojian
    Marimuthu, Pandi C.
    [J]. 2012 13TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2012), 2012, : 151 - 156
  • [29] Wafer Level Package Wafer Probing Shift Error-Proof Quality Control
    Jin, Morn
    He, Wenwen
    Qiao, John
    Chien, Wei-Ting Kary
    Zhao, Shirley
    [J]. 2015 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL ENGINEERING AND ENGINEERING MANAGEMENT (IEEM), 2015, : 939 - 942
  • [30] Development of liquid molding compound for fan-out wafer level package
    Kan, Katsushi
    Oi, Yosuke
    Fujii, Yasuhito
    [J]. Journal of Japan Institute of Electronics Packaging, 2020, 23 (06) : 501 - 506