High-speed and Huge-capacity Data Cache System Based on FPGA

被引：0

作者：

Gao, Fei ^{[1
]}

Chang, Wenge ^{[1
]}

Li, Xiangyang ^{[1
]}

机构：

[1] Natl Univ Def Technol, Changsha 410073, Hunan, Peoples R China

来源：

PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING, INFORMATION SCIENCE & APPLICATION TECHNOLOGY (ICCIA 2016) | 2016年 / 56卷

关键词：

Cache; High-speed; Huge-capacity; DDR3; RapidIO;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Aiming at the high-speed and huge-capacity data cache and transmission caused by real-time signal processor for high-resolution SAR, this paper presents a design for the high-speed and huge-capacity data acquisition system based on DDR3 SDRAM and RapidIO. Data cache is realized by MIG3.92 IP core in Xilinx Virtex_6 series FPGA. Data Transmission is realized by RapidIO IP core and GTX. The testing results show that the maximum write rate of DDR3 memory is 3120MB/s and the transmission rate of RapidIO interface is 1800 MB/s.

引用

页码：306 / 310

页数：5

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