High-speed and Huge-capacity Data Cache System Based on FPGA

被引：0

作者：

Gao, Fei ^{[1
]}

Chang, Wenge ^{[1
]}

Li, Xiangyang ^{[1
]}

机构：

[1] Natl Univ Def Technol, Changsha 410073, Hunan, Peoples R China

来源：

PROCEEDINGS OF THE 2016 INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING, INFORMATION SCIENCE & APPLICATION TECHNOLOGY (ICCIA 2016) | 2016年 / 56卷

关键词：

Cache; High-speed; Huge-capacity; DDR3; RapidIO;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

Aiming at the high-speed and huge-capacity data cache and transmission caused by real-time signal processor for high-resolution SAR, this paper presents a design for the high-speed and huge-capacity data acquisition system based on DDR3 SDRAM and RapidIO. Data cache is realized by MIG3.92 IP core in Xilinx Virtex_6 series FPGA. Data Transmission is realized by RapidIO IP core and GTX. The testing results show that the maximum write rate of DDR3 memory is 3120MB/s and the transmission rate of RapidIO interface is 1800 MB/s.

引用

页码：306 / 310

页数：5

共 50 条

[41] High-Speed Communication System Development using FPGA based CAM Implementation
Banerjee, Tribeni Prasad
Konar, Amit
Chowdhury, Joydeb Roy
[J]. 2009 SECOND INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET 2009), 2009, : 252 - +
[42] FPGA based high-speed system solutions for innovative maskless lithography systems
Voss, Sven-Hendrik
Talmi, Maati
[J]. PHOTOMASK AND NEXT GENERATION LITHOGRAPHY MASK TECHNOLOGY XIII, PTS 1 AND 2, 2006, 6283
[43] Large-Capacity and High-Speed Instruction Cache Based on Divide-by-2 Memory Banks
Li, Qing-Qing
Yu, Zhi-Guo
Sun, Yi
Wei, Jing-He
Gu, Xiao-Feng
[J]. Journal of Electronic Science and Technology, 2021, 19 (04) : 335 - 349
[44] Large-Capacity and High-Speed Instruction Cache Based on Divide-by-2 Memory Banks
Qing-Qing Li
Zhi-Guo Yu
Yi Sun
Jing-He Wei
Xiao-Feng Gu
[J]. Journal of Electronic Science and Technology, 2021, (04) : 335 - 349
[45] Large-Capacity and High-Speed Instruction Cache Based on Divide-by-2 Memory Banks
QingQing Li
ZhiGuo Yu
Yi Sun
JingHe Wei
XiaoFeng Gu
[J]. Journal of Electronic Science and Technology, 2021, 19 (04) - 349
[46] HIGH-SPEED DATA TERMINAL SYSTEM
ADACHI, K
KONDO, Y
YONENO, K
[J]. JAPAN TELECOMMUNICATIONS REVIEW, 1975, 17 (03): : 205 - 214
[47] High-speed flow-based classification on FPGA
Groleat, Tristan
Vaton, Sandrine
Arzel, Matthieu
[J]. INTERNATIONAL JOURNAL OF NETWORK MANAGEMENT, 2014, 24 (04) : 253 - 271
[48] The Design and Implementation of High-Speed Codec Based on FPGA
Ren, Weiji
Liu, Hao
[J]. 2018 10TH INTERNATIONAL CONFERENCE ON COMMUNICATION SOFTWARE AND NETWORKS (ICCSN), 2018, : 427 - 432
[49] High-speed Arbitrary Waveform Generator based on FPGA
Zhang, Hong-Fei
Luo, Chun-Li
Tang, Peng-Yi
Cui, Ke
Lin, Sheng-Zhao
Jin, Ge
Wang, Jian
[J]. 2013 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE (NSS/MIC), 2013,
[50] PCI bus based high-speed data acquisition system
Yang, RF
Li, JP
[J]. ISTM/2003: 5TH INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, VOLS 1-6, CONFERENCE PROCEEDINGS, 2003, : 559 - 561

← 1 2 3 4 5 →