Performance Limit of Gate-All-Around Si Nanowire Field-Effect Transistors: An Ab Initio Quantum Transport Simulation

The gate-all-around (GAA) Si nanowire (NW) field-effect transistor (FET) is considered one of the most promising successors of the current mainstream Si fin FET (FinFET) owing to its better electrostatic gate control. Experimentally, the diameter of Si NWs has been scaled down to 1 nm. In this paper, the performance limit of the GAA Si NWFET with a 1-nm diameter is investigated by utilizing ab initio quantum transport simulations. We prove that the electrical conduction is concentrated in the core of the ultranarrow wire channel. The minimum gate length (L-g) at which the n- and p-type GAA Si NWFET can satisfy the high-performance application requirements (on-state current, gate capacitance, delay time, and power dissipation) of the International Technology Roadmap for Semiconductors is 3 nm. The best-performing 5-nm-Lg n-type GAA Si NWFET exhibits an energy-delay product comparable with typical monolayer two-dimensional FETs. Compared with the similar-sized trigate Si NW FinFET, an approximately 200% increase in the on-state current and about 15% decrease in the subthreshold swing are witnessed in GAA Si NWFET at the same 5-nm Lg. Through strain engineering, about an 80% increase of on-state current is observed in the 5-nm-Lg p-type GAA Si NWFET. Our research demonstrates the vast potential of the GAA Si NWFET in the sub-3-nm gate-length region.