Electrostatic Discharge (ESD) Protection Challenges of Gate-All-Around Nanowire Field-Effect Transistors

被引：0

作者：

Liu, W. ^{[1
]}

Liou, J. J. ^{[1
]}

Singh, N. ^{[2
]}

Lo, G. Q. ^{[2
]}

Chung, J. ^{[3
]}

Jeong, Y. H. ^{[3
]}

机构：

[1] Univ Cent Florida, Sch EECS, Orlando, FL 32816 USA

[2] ASTAR, Inst Microelect, Singapore, Singapore

[3] Pohang Univ Sci & Technol, Pohang, South Korea

来源：

CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011) | 2011年 / 34卷 / 01期

关键词：

DEVICES;

D O I：

10.1149/1.3567559

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Electrostatic discharge (ESD) performance, including trigger voltage, failure current, on-resistance and leakage current, of the gate-all-around silicon nanowire field-effect transistor depends on nanowire diameter, gate length and nanowire numbers. The device with best ESD robustness has medium gate length, small diameter and a large number of nanowires with multi-finger-multi-channel layout.

引用

页码：55 / 60

页数：6

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