Delay-locked loop with correlation branch selection

被引:0
|
作者
Wilde, A
机构
关键词
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In spread spectrum systems the delay-locked loop (DLL) is widely used to track the spreading code. Normally a design tradeoff between tracking accuracy and robustness against disturbances Is required. Extended tracking range DLLs (ExtDLL) using more than two correlators increase the robustness but are less accurate. An algorithm based on the ExtDLL is proposed offering both robustness and good accuracy by selecting only correlation branches with an useful control signal. The new algorithm shows a very good performance at medium to high signal-to-noise ratios (SNR). With increasing SNR it approaches the classical DLL performance for accuracy and is more robust than the classical DLL and the ExtDLL.
引用
收藏
页码:614 / 618
页数:5
相关论文
共 50 条
  • [31] A fractional delay-locked loop for on chip clock generation applications
    Torkzadeh, P.
    Tajalli, A.
    Atarodi, M.
    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 1300 - 1303
  • [32] A novel delay-locked loop based CMOS clock multiplier
    Birru, D
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, 1998, 44 (04) : 1319 - 1322
  • [33] A 133 MHz Radiation-Hardened Delay-Locked Loop
    Sengupta, Rajat
    Vermeire, Bert
    Clark, Lawrence T.
    Bakkaloglu, Bertan
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2010, 57 (06) : 3626 - 3633
  • [34] A Check-and-Balance Scheme in Multiphase Delay-Locked Loop
    Chang, Shu-Yu
    Huang, Shi-Yu
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, 32 (07) : 1253 - 1262
  • [35] PLD Implementation of All-digital Delay-Locked Loop
    Matic, Tomislav
    Svedek, Tomislav
    Herceg, Marijan
    PROCEEDINGS ELMAR-2008, VOLS 1 AND 2, 2008, : 249 - 252
  • [36] Design of Delay-Locked Loop for Wide Frequency Locking Range
    Chen, Hsun-Hsiang
    Wong, Zih-Hsiang
    Chen, Shen-Li
    2013 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2013, : 302 - 305
  • [37] A 155-MHZ CLOCK RECOVERY DELAY-LOCKED AND PHASE-LOCKED LOOP
    LEE, TH
    BULZACCHELLI, JF
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (12) : 1736 - 1746
  • [38] A dual-loop delay-locked loop using multiple voltage-controlled delay lines
    Jung, YJ
    Lee, SW
    Shim, D
    Kim, W
    Kim, C
    Cho, SI
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (05) : 784 - 791
  • [39] Spatial-phase-locked electron-beam lithography with a delay-locked loop
    Goodberlet, J
    Ferrera, J
    Smith, HI
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1997, 15 (06): : 2293 - 2297
  • [40] A Multiphase All-Digital Delay-Locked Loop with Reuse SAR
    Chen, Pao-Lung
    Wang, Tzu-Siang
    Ciou, Jyun-Han
    PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS), 2010, : 939 - 942