PLD Implementation of All-digital Delay-Locked Loop

被引：0

作者：

Matic, Tomislav ^{[1
]}

Svedek, Tomislav ^{[1
]}

Herceg, Marijan ^{[1
]}

机构：

[1] JJ Strossmayer Univ Osijek, Fac Elect Engn, Dept Commun, Osijek, Croatia

来源：

PROCEEDINGS ELMAR-2008, VOLS 1 AND 2 | 2008年

关键词：

PLD; All-digital Delay-Locked Loop;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An all-digital delay-locked loop (DLL) suitable for implementation in programmable logic devices (PLD) is presented in this paper. All parts of DLL are created only from discrete digital elements. A digital controlled delay line (DCDL) is made from digital controlled delay elements (DCDE) by using LCELL (basic delay elements in ALTERA). A charge pump (CP) and a loop filler (LF) in the proposed circuit are replaced with a 3-bit up/down/hold counter. The proposed DLL is implemented and tested in ALTERA PLD EPM7128SLI10.

引用

页码：249 / 252

页数：4

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