共 50 条
- [41] Wafer Level Underfill Study for High Density Ultra-fine Pitch Cu-Cu Bonding for 3D IC Stacking 2014 IEEE 16TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2014, : 400 - 404
- [42] Improvements of solder ball shear strength of a wafer-level CSP using a novel Cu stud technology IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2004, 27 (02): : 373 - 382
- [44] D-Band Flip-Chip Packaging with Wafer-Level Cu-pillar Bumps 2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS, 2023,
- [45] Package- and wafer-level electromigration tests on Al-Cu interconnect with Ti and TiN underlayers Metals and Materials International, 2001, 7 (05): : 493 - 498
- [49] Solid-State-Diffusion Bonding for Wafer-Level Fine-Pitch Cu/Sn/Cu Interconnect in 3-D Integration IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2017, 7 (01): : 19 - 26
- [50] Wafer-level 3D system-on-a-chip using dielectric glue wafer bonding and Cu damascene inter-wafer interconnects SEMICONDUCTOR WAFER BONDING VII: SCIENCE, TECHNOLOGY, AND APPLICATIONS, PROCEEDINGS, 2003, 2003 (19): : 87 - 95