The Design of a Hardware Thread Manager for a Polymorphic Multimedia Processor

被引：0

作者：

Qian, Bowen ^{[1
]}

Li, Tao ^{[1
]}

Yang, Ting ^{[2
]}

机构：

[1] Xian Univ Posts & Telecommun, Sch Elect Engn, Xian, Peoples R China

[2] Xian Univ Posts & Telecommun, Sch Comp, Xian, Peoples R China

来源：

PROCEEDINGS OF 3RD INTERNATIONAL CONFERENCE ON MULTIMEDIA TECHNOLOGY (ICMT-13) | 2013年 / 84卷

基金：

美国国家科学基金会;

关键词：

Many core; Multithreading; Array processor; Parallel processing; Graphics and Multimedia;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes a hardware thread manager for the polymorphic parallel processor. The thread manager supports the MIMD mode with 8 threads and SIMD mode with multiple threads using the SIMD controllers in a unified approach to manage two operating modes to achieve a mixture of three types of parallel computation. Thread manager monitors the progress of each thread, the activity of near neighbor shared memory and the status of the router. It schedules the execution slots for the threads. It can start and stop a thread, put a thread on wait, resume the execution of a thread. Thread manager can also record the working status of each thread, while avoiding the waiting problem caused by data availability. This manager is able to maximize the efficiency of a processing element in a polymorphic array processor.

引用

页码：1792 / 1799

页数：8

共 50 条

[1] Router Design and Implementation for a Polymorphic Multimedia Processor
Yang, Ting
Li, Tao
Wang, Ya-Gang
Qian, Bo-Wen
Liu, Yu-Rong
PROCEEDINGS OF 3RD INTERNATIONAL CONFERENCE ON MULTIMEDIA TECHNOLOGY (ICMT-13), 2013, 84 : 1292 - 1300
[2] On networking multithreaded processor design:: Hardware thread prioritization
Döring, A
Gabrani, M
Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 2003, : 520 - 523
[3] Hardware design and evaluation of the FUCE processor for thread level parallel processing
Matsuzaki, Takanori
Amamiya, Satoshi
Izumi, Masaaki
Amamiya, Makoto
Research Reports on Information Science and Electrical Engineering of Kyushu University, 2006, 11 (01): : 39 - 44
[4] Design of a hardware security-embedded multimedia mobile processor
Fukase, MA
Sato, Y
Sato, T
IEEE INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES 2004 (ISCIT 2004), PROCEEDINGS, VOLS 1 AND 2: SMART INFO-MEDIA SYSTEMS, 2004, : 362 - 367
[5] Design and Hardware Implementation of QoSS-AES Processor for Multimedia applications
Medien, Zeghid
Machhout, Mohsen
Bouallegue, Belgacem
Khriji, Lazhar
Baganne, Adel
Tourki, Rached
TRANSACTIONS ON DATA PRIVACY, 2010, 3 (01) : 43 - 64
[6] Hardware support for arithmetic units of processor with multimedia extension
Huang, Libo
Lai, Mingche
Dai, Kui
Yue, Hong
Shen, Li
MUE: 2007 INTERNATIONAL CONFERENCE ON MULTIMEDIA AND UBIQUITOUS ENGINEERING, PROCEEDINGS, 2007, : 633 - +
[7] Multimedia data processing using a VLIW hardware stack processor
Nakamura, Kiyoshige
Sakai, Keiichi
Ae, Tadashi
Systems and Computers in Japan, 1999, 30 (10): : 34 - 40
[8] Design and implementation of a scalable multimedia processor
Dassatti, A
Martina, M
Masera, G
Molino, A
Piccinini, G
Vacca, F
Zamboni, M
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2003, : 89 - 92
[9] A methodology to design a multimedia processor core
Ramazani, A
Monteiro, E
Dandache, A
Lepley, B
ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 998 - 1001
[10] A methodology to design a multimedia processor core
1600, Emirates Telecommunications Corporation (ETISALAT); Etisalat College of Engineering (ECE); IEEE Circuits and Systems Society (CAS); Institute of Electrical and Electronics Engineers (IEEE); University of Sharjah (UOS) (Institute of Electrical and Electronics Engineers Inc., United States):

← 1 2 3 4 5 →