Hardware support for arithmetic units of processor with multimedia extension

被引：0

作者：

Huang, Libo ^{[1
]}

Lai, Mingche ^{[1
]}

Dai, Kui ^{[1
]}

Yue, Hong ^{[1
]}

Shen, Li ^{[1
]}

机构：

[1] Natl Univ Def Technol, Changsha 410073, Peoples R China

来源：

MUE: 2007 INTERNATIONAL CONFERENCE ON MULTIMEDIA AND UBIQUITOUS ENGINEERING, PROCEEDINGS | 2007年

关键词：

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Multimedia extension technique is very popular in designing processors to improve multimedia processing performance. This paper carries on the study of hardware implementation of arithmetic units with multimedia extension support, and proposes new design methods for subword multiplier and SIMD (Single Instruction Multiple Data) IEEE FPU (Floating-Point Unit). To verify the correctness and effectiveness of these methods, a multimedia co-processor with SIMD fixed-point and floating-point units is designed. The implemented chip successfully demonstrates that the proposed SIMD Arithmetic units get good trade off between cost and performance.

引用

页码：633 / +

页数：2

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