Built-in self test for content addressable memories

被引:0
|
作者
Kang, YS
Lee, JC
Kang, SH
机构
来源
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS | 1997年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A new parallel test algorithm and a Built-in Self Test(BIST) architecture far an efficient testing of various types of functional faults in Content Addressable Memories(CAMs) are developed. fn test mode, the read operation is replaced by one parallel content addressable search operation and the writing operation is performed parallely with small peripheral circuit modifications. The results show that an efficient and practical testing with very low complexity and area overhead can be achieved.
引用
收藏
页码:48 / 53
页数:6
相关论文
共 50 条
  • [21] Economics of built-in self-test
    Ungar, LY
    Ambler, T
    IEEE DESIGN & TEST OF COMPUTERS, 2001, 18 (05): : 70 - 79
  • [22] BUILT-IN SELF-TEST TECHNIQUES
    MCCLUSKEY, EJ
    IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (02): : 21 - 28
  • [23] Built-In Self-Repair Schemes for Flash Memories
    Hsiao, Yu-Ying
    Chen, Chao-Hsun
    Wu, Cheng-Wen
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (08) : 1243 - 1256
  • [24] Optimized Built-In Self-Repair for Multiple Memories
    Kang, Wooheon
    Lee, Changwook
    Lim, Hyunyul
    Kang, Sungho
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (06) : 2174 - 2183
  • [25] On Built-In Self-Test for Multipliers
    Pulukuri, Mary D.
    Starr, George J.
    Stroud, Charles E.
    IEEE SOUTHEASTCON 2010: ENERGIZING OUR FUTURE, 2010, : 25 - 28
  • [26] On Built-In Self-Test for Adders
    Pulukuri, Mary D.
    Stroud, Charles E.
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2009, 25 (06): : 343 - 346
  • [27] 1984 BUILT-IN SELF TEST WORKSHOP
    SEDMAK, R
    RADKE, C
    IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (01): : 78 - 79
  • [28] On Built-In Self-Test for Adders
    Mary D. Pulukuri
    Charles E. Stroud
    Journal of Electronic Testing, 2009, 25 : 343 - 346
  • [29] DESIGN OF MODIFIED MARCH-C ALGORITHM AND BUILT-IN SELF-TEST ARCHITECTURE FOR MEMORIES
    Karthy, G.
    Sivakumar, P.
    3C TECNOLOGIA, 2020, (SI): : 219 - 229
  • [30] Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories
    Sable, RS
    Saraf, RP
    Parekhji, RA
    Chandorkar, AN
    17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 753 - 756