On Built-In Self-Test for Adders

We evaluate some of the previously proposed test approaches for various types of adders in an attempt to find an architecture-independent algorithm for testing adders in embedded Digital Signal Processors (DSPs) in Field Programmable Gate Arrays (FPGAs). We find that a minor modification to a previously proposed Built-In Self-Test (BIST) approach provides the highest fault coverage for most types of adders and, equally important, it is simple to implement.