A 160MHz-to-2GHz Low Jitter Fast Lock All-Digital DLL with Phase Tracking Technique

被引：0

作者：

Hung, Shuo-Hong ^{[1
]}

Kao, Wei-Hao ^{[1
]}

Wu, Kuan-I ^{[1
]}

Huang, Yi-Wei ^{[1
]}

Hsieh, Min-Han ^{[1
]}

Chen, Charlie Chung -Ping ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

来源：

2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An all-digital delay-locked loop (ADDLL) is proposed for wide range, fast lock, low jitter and high process-voltage-temperature (PVT) tolerance. The proposed phase tracking generator (PTG) produces two tracking rising and falling phases in only 2 cycles for fast lock and wide-range. The digital phase interpolator (DPI) and the control block are adopted to calibrate the phase offsets and random jitters while maintaining the closed-loop property that allow for tracking of PVT variations. The wide-range ADDLL operates from 160MHz to 2GHz. The measured peak-to-peak jitters are 6.89ps and 16.67ps at 2GHz and 160MHz. This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.205mm(2).

引用

页码：553 / 556

页数：4

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