A 160MHz-to-2GHz Low Jitter Fast Lock All-Digital DLL with Phase Tracking Technique

被引：0

作者：

Hung, Shuo-Hong ^{[1
]}

Kao, Wei-Hao ^{[1
]}

Wu, Kuan-I ^{[1
]}

Huang, Yi-Wei ^{[1
]}

Hsieh, Min-Han ^{[1
]}

Chen, Charlie Chung -Ping ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan

来源：

2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An all-digital delay-locked loop (ADDLL) is proposed for wide range, fast lock, low jitter and high process-voltage-temperature (PVT) tolerance. The proposed phase tracking generator (PTG) produces two tracking rising and falling phases in only 2 cycles for fast lock and wide-range. The digital phase interpolator (DPI) and the control block are adopted to calibrate the phase offsets and random jitters while maintaining the closed-loop property that allow for tracking of PVT variations. The wide-range ADDLL operates from 160MHz to 2GHz. The measured peak-to-peak jitters are 6.89ps and 16.67ps at 2GHz and 160MHz. This chip is fabricated in TSMC 90nm CMOS technology with an active area of 0.205mm(2).

引用

页码：553 / 556

页数：4

共 50 条

[41] A fast locked and low phase noise all-digital phase locked loop based on model predictive control
Mohamad Sayadi
Ebrahim Farshidi
Analog Integrated Circuits and Signal Processing, 2016, 88 : 401 - 414
[42] A fast phase tracking reference-less all-digital CDR circuit for human body channel communication
Chung, Ching-Che
Sheng, Duo
Li, Ming-Chieh
Tsai, Yi-Che
MICROELECTRONICS JOURNAL, 2019, 84 : 87 - 95
[43] A 0.68-to-1.44 GHz Low-Jitter All-Digital Phase-Locked Loop with A Novel PFD and A High Resolution DCO in 0.18μm CMOS
Deng, Xiaoying
Mo, Yanyan
Lin, Xin
Zhu, Mingcheng
2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2016, : 104 - 107
[44] A 1.25GHz Fast-Locked All-Digital Phase-Locked Loop with Supply Noise Suppression
Hung, Chao-Ching
Chen, I-Fong
Liu, Shen-Iuan
2010 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN AUTOMATION AND TEST (VLSI-DAT), 2010, : 237 - 240
[45] An improved phase digitization mechanism for fast-locking low-power all-digital PLLs
Xie, Lin-lin
Wang, Yang
Qiao, Shu-shan
Hei, Yong
IEICE ELECTRONICS EXPRESS, 2017, 14 (21):
[46] A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique
Chen, Xin
Yang, Jun
Shi, Long-Xing
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (05) : 857 - 868
[47] A LOW-POWER HIGH-RESOLUTION ALL-DIGITAL ON-CHIP JITTER SENSOR FOR A 1-3 GHZ CLOCK GENERATOR
Chou, Pei-Yuan
Lin, Wei-Ling
Cheng, Chiang Hu
Lin, Tay-Jyi
Wang, Jyh-Herng
Wang, Jinn-Shyan
2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 693 - 695
[48] A 0.17-1.4GHz Low-Jitter All Digital DLL with TDC-based DCC using Pulse Width Detection Scheme
Shin, Dongsuk
Yun, Won-Joo
Lee, Hyun-Woo
Choi, Young-Jung
Kim, Suki
Kim, Chulwoo
ESSCIRC 2008: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2008, : 82 - +
[49] A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology
Yun, Won-Joo
Lee, Hyun-Woo
Shin, Dongsuk
Kim, Suki
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (09) : 1718 - 1722
[50] An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking
Rehman, Muhammad Riaz Ur
Hejazi, Arash
Ali, Imran
Asif, Muhammad
Oh, Seongjin
Kumar, Pervesh
Pu, Younggun
Yoo, Sang-Sun
Hwang, Keum Cheol
Yang, Youngoo
Jung, Yeonjae
Huh, Hyungki
Kim, Seokkee
Yoo, Joon-Mo
Lee, Kang-Yoon
IEEE ACCESS, 2021, 9 : 152984 - 152992

← 1 2 3 4 5 →