A high-speed, programmable, CSD coefficient FIR filter

被引：2

作者：

Tang, ZW ^{[1
]}

Zhang, ZP ^{[1
]}

Zhang, J ^{[1
]}

Min, H ^{[1
]}

机构：

[1] Fudan Univ, ASIC & Syst State Key Lab, Shanghai 200433, Peoples R China

来源：

2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS | 2001年

关键词：

terms-finite impulse response filter; application specific integrated circuit; canonic signed-digit encode; booth multiplier; wallace adder tree;

D O I：

10.1109/ICASIC.2001.982584

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A new high-speed, programmable FIR filter is present, which is a multiplierless filter with CSD encoding coefficients. With this encoding scheme, the speed of filter is improved and the area Is optimized. In order to make this filter more applicable, we employ a new programmable CSD encoding structure to make CSD coefficients programmable. In the end of this paper, we design a 10-bits, 18 taps video luminance filter with the filter structure we present. The completed filter core occupies 6.8x6.8 mm(2) of silicon area in Wu-Xi Shanghua 0.6-mum 2P2M CMOS technology, and its maximum work frequency is 100MHz.

引用

页码：397 / 400

页数：4

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