Stress-Induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7nm Technology Nodes

The epitaxially grown SiGe source/drain stressor (e-SiGe) technique has emerged to be a consistent performance booster for advanced devices below the 14nm technology node. At nanoscale, the omnipresent residual stress is now becoming an important source of variability in advanced VLSI technologies that influence the circuit performance. Also, in deeply-scaled technologies, process and environment variations become other sources of variabilities. In this paper, we study the stress-induced variability in aggressively scaled (at 7N) Si-channel FinFETs with epitaxially grown SiGe stressors in the source and drain regions. The stress distribution analysis is performed with the help of Technology CAD mechanical stress simulations. At first, we calibrate our simulation results with available experimental data. We generate the stress maps in FinFETs with various scaled dimensions of fin length, height and width. The effects of residual strain/stress on variability due to metal gate granularity (MGG) and random discrete dopant (RDD) in strain-engineered FinFETs (with 50 configurations) have been investigated. Furthermore, the device threshold voltage variation due to RDD and MGG are critically examined. Finally, we calculate the mean and standard deviation of these parameters (QQ plots) to quantify the variability.