Electrostatics and Performance Benchmarking using all types of III-V Multi-gate FinFETs for sub 7nm Technology Node Logic Application

被引：0

作者：

Baek, R. -H. ^{[1
]}

Kim, D. -H. ^{[1
,2
]}

Kim, T. -W. ^{[1
]}

Shin, C. S. ^{[3
]}

Park, W. K. ^{[3
]}

Michalak, T. ^{[4
]}

Borst, C. ^{[4
]}

Song, S. C. ^{[5
]}

Yeap, Geoffrey ^{[5
]}

Hill, R. ^{[1
]}

Hobbs, C. ^{[1
]}

Maszara, W. ^{[2
]}

Kirsch, P. ^{[1
]}

机构：

[1] SEMATECH, 257 Fuller Rd, Albany, NY 12203 USA

[2] GLOBALFOUNDRIES, Milpitas, CA USA

[3] KANC, North Conway, NH USA

[4] CNSE, Albany, NY USA

[5] QUALCOMM, San Diego, CA USA

来源：

2014 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI-TECHNOLOGY): DIGEST OF TECHNICAL PAPERS | 2014年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we conducted the sub 7nm technology benchmarking for logic application using performance comparison between III-V multi-gate(double, tri, gate-all-around) nMOSFET and Si nFinFET. The benchmarking was executed based on the physical parameters extracted from Virtual-Source(VS) modeling and well-calibrated TCAD simulation. Especially by quantitatively investigating fin width(Wfin) and interface trap(Dit) effects on electrostatic of III-V multi-gate(MG) nMOSFET which is critical to device scaling, we proposed a device design strategy for sub 7nm technology node.

引用

页数：2

共 6 条

[1] Comprehensive Layout and Process Optimization Study of Si and III-V Technology for sub-7nm Node
Kang, C. Y.
Baek, R-H.
Kim, T-W
Ko, D.
Kim, D-H.
Michalak, T.
Borst, C.
Veksler, D.
Bersuker, G.
Hill, R.
Hobbs, C.
Kirsch, P. D.
[J]. 2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
[2] High-performance logic transistor DC benchmarking toward 7 nm technology-node between III-V and Si tri-gate n-MOSFETs using virtual-source injection velocity model
Baek, Rock-Hyun
Kim, Jin Su
Kim, Do-Kywn
Kim, Taewoo
Kim, Dae-Hyun
[J]. SOLID-STATE ELECTRONICS, 2016, 116 : 100 - 103
[3] Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices
Valasa, Sresta
Ramakrishna, K. V.
Bhukya, Sunitha
Narware, Pallavi
Bheemudu, V.
Vadthiya, Narendar
[J]. ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2023, 12 (11)
[4] Performance Comparison Between Inversion Mode and Junctionless Cylindrical Gate All Around Si Nanowire MOSFET Using Dual Metal Gate Work Function Engineering for Upcoming Sub 5 nm Technology Node
Vibhor Sanjay
Anil Kumar
[J]. Silicon, 2024, 16 : 989 - 1003
[5] Performance Comparison Between Inversion Mode and Junctionless Cylindrical Gate All Around Si Nanowire MOSFET Using Dual Metal Gate Work Function Engineering for Upcoming Sub 5 nm Technology Node
Sanjay, Vibhor
Kumar, Vibhor
Vohra, Anil
[J]. SILICON, 2024, 16 (03) : 989 - 1003
[6] DC and Analog/RF Performance Evaluation Using Dual Metal Gate Work Function Engineering of Junctionless Cylindrical Gate All Around Si Nanowire MOSFET Using NEGF Approach for Upcoming Sub 5 nm Technology Node
Sanjay
Kumar, Vibhor
Vohra, Anil
[J]. INTERNATIONAL JOURNAL OF PRECISION ENGINEERING AND MANUFACTURING, 2024, 25 (09) : 1885 - 1897

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