STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process

被引：0

作者：

Jang, Doyoung ^{[1
]}

Bardon, Marie Garcia ^{[1
]}

Yakimets, Dmitry ^{[1
]}

Miyaguchi, Kenichi ^{[1
]}

De Keersgieter, An ^{[1
]}

Chiarella, Thomas ^{[1
]}

Ritzenthaler, Romain ^{[1
]}

Dehan, Morin ^{[1
]}

Mercha, Abdelkarim ^{[1
]}

机构：

[1] IMEC, B-3001 Heverlee, Belgium

来源：

2013 PROCEEDINGS OF THE EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As CMOS technology goes into the nanoscale regime, the impact of layout on the device performance becomes increasingly important. In this paper, we propose a physics-based analytical model for Layout Dependent Effects (LDE) due to shallow trench isolation (STI) stress in 28 nm technology using "gate-last" process (Replacement Gate - RMG). The impact of active size and active width are considered and the model links between stress and device parameters such as the mobility and threshold voltage. The model is validated with experimental data. In addition, we investigate the impact of embedded Silicon-Germanium source/drain (eSiGe S/D) stressors in PMOS. Stronger mobility degradation is predicted for small width devices once eSiGe S/D is used. It results in a larger drop of normalized current (mu A/mu m) (-16%) once compared to transistors without eSiGe (-7%)

引用

页码：159 / 162

页数：4

共 7 条

[1] Stress-Induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7 nm Technology Nodes
T. P. Dash
J. Jena
E. Mohapatra
S. Dey
S. Das
C. K. Maiti
[J]. Journal of Electronic Materials, 2019, 48 : 5348 - 5362
[2] Stress-Induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7nm Technology Nodes
Dash, T. P.
Jena, J.
Mohapatra, E.
Dey, S.
Das, S.
Maiti, C. K.
[J]. JOURNAL OF ELECTRONIC MATERIALS, 2019, 48 (08) : 5348 - 5362
[3] Modeling of STI-induced stress phenomena in CMOS 90nm Flash technology
Fantini, P
Giuga, G
Schippers, S
Marmiroli, A
Ferrari, G
[J]. ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2004, : 401 - 404
[4] Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology
Sun, Lijie
Shang, Ganbing
Liu, Linlin
Cheng, Jia
Guo, Ao
Ren, Zheng
Hu, Shaojian
Chen, Shoumian
Zhao, Yuhang
Chan, Mansun
Zhang, Long
Li, Xiaojin
Shi, Yanling
[J]. SOLID-STATE ELECTRONICS, 2015, 111 : 118 - 122
[5] Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension
Kaneko, A
Yagishita, A
Yahashi, K
Kubota, T
Omura, M
Matsuo, K
Mizushima, I
Okano, K
Kawasaki, H
Inaba, S
Izumida, T
Kanemura, T
Aoki, N
Ishimaru, K
Ishiuchi, H
Suguro, K
Eguchi, K
Tsunashima, Y
[J]. IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 863 - 866
[6] Intrinsic Dielectric Stack Reliability of a High Performance Bulk Planar 20nm Replacement Gate High-K Metal Gate Technology and Comparison to 28nm Gate First High-K Metal Gate Process
McMahon, W.
Tian, C.
Uppal, S.
Kothari, H.
Jin, M.
LaRosa, G.
Nigam, T.
Kerber, A.
Linder, B. P.
Cartier, E.
Lai, W. L.
Liu, Y.
Ramachandran, R.
Kwon, U.
Parameshwaran, B.
Krishnan, S.
Narayanan, V.
[J]. 2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2013,
[7] Tr variance evaluation induced by probing pressure and its stress extraction methodology in 28nm High-K and Metal Gate process
Okagaki, T.
Hasegawa, T.
Takashino, H.
Fujii, M.
Tsuda, A.
Shibutani, K.
Deguchi, Y.
Yokota, M.
Onozawa, K.
[J]. 2013 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES (ICMTS), 2013, : 203 - 206

← 1 →