MULTI-CORE SOFTWARE ARCHITECTURE FOR THE SCALABLE HEVC DECODER

被引：0
|
作者：
Hamidouche, Wassim [1 ]
Raulet, Mickael [1 ]
Deforges, Olivier [1 ]
机构：
[1] UEB, UMR 6164, IETR INSA, F-35708 Rennes, France
来源：
2014 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP) | 2014年
关键词：
HEVC; Scalable HEVC; High level parallel processing and wavefront parallel processing; VIDEO CODING EXTENSION;
D O I：
暂无
中图分类号：
O42 [声学];
学科分类号：
070206 ; 082403 ;
摘要：
The scalable high efficiency video coding (SHVC) standard aims to provide features of temporal, spatial and quality scalability. In this paper we investigate a pipeline and parallel software architecture for the SHVC decoder. The proposed architecture is based on the OpenHEVC software which implements the high efficiency video coding (HEVC) decoder. The architecture of the SHVC decoder enables two levels of parallelism. The first level decodes the base layer and the enhancement layers in parallel. The second level of parallelism performs the decoding of both the base layer and enhancement layers in parallel through the HEVC high level parallel processing solutions, including tile and wavefront. Up to the best of our knowledge, it is the first real time and parallel software implementation of the SHVC decoder. On an Intel Xeon processor running at 3.2 GHz, the SHVC decoder reaches the decoding of 1600p enhancement layer at 40 fps for x1.5 spatial scalability with using six concurent threads.
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页数：5
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