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An efficient test relaxation technique for combinational & full-scan sequential circuits

被引：52
|
作者：
El-Maleh, A [1 ]
Al-Suwaiyan, A [1 ]
机构：
[1] King Fahd Univ Petr & Minerals, Dhahran 31261, Saudi Arabia
来源：
20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/VTS.2002.1011111
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.
引用
收藏
页码：53 / 59
页数：7
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