Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation

被引：3

作者：

Doi, Yasumi ^{[1
]}

Kajihara, Seiji ^{[1
]}

Wen, Xiaoqing ^{[1
]}

Li, Lei ^{[1
]}

Chakrabarty, Krishnendu ^{[1
]}

机构：

[1] Kyushu Inst Technol, Dept Comp Sci & Elect, Iizuka, Fukuoka 8208502, Japan

来源：

ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2005年

关键词：

D O I：

10.1145/1120725.1120744

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a test compression method that effectively derives the capability of a run-length based encoding. The method employs two techniques: scan polarity adjustment and pinpoint test relaxation. Given a test set for a full-scan circuit, scan polarity adjustment selectively flips the values of some scan cells in test patterns. It can be realized by changing connections between two scan cells so that the inverted output of a scan cell, Q, is connected to the next scan cell. Pinpoint test relaxation flips some specified is in the test patterns to Os without any fault coverage loss. Both techniques are applied by referring to a gain-penalty table to determine scan cells or bits to be flipped. Experimental results on ISCAS' 89 benchmark circuits show that the proposed method could reduce test data volume by 36%. Switching activities, i.e. test power during scan testing, were also reduced.

引用

页码：59 / 64

页数：6

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