An efficient test relaxation technique for combinational & full-scan sequential circuits

被引：52
|
作者：
El-Maleh, A [1 ]
Al-Suwaiyan, A [1 ]
机构：
[1] King Fahd Univ Petr & Minerals, Dhahran 31261, Saudi Arabia
来源：
20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/VTS.2002.1011111
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper, we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.
引用
收藏
页码：53 / 59
页数：7
相关论文
共 50 条
  • [1] Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences
    Pomeranz, I
    Reddy, SM
    [J]. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2003, : 335 - 340
  • [2] Static test compaction for multiple full-scan circuits
    Pomeranz, I
    Reddy, SM
    [J]. 21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, : 393 - 396
  • [3] ATPG for dynamic burn-in test in full-scan circuits
    Benso, Alfredo
    Bosio, Alberto
    Di Carlo, Stefano
    Di Natale, Giorgio
    Prinetto, Paolo
    [J]. PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM, 2006, : 75 - +
  • [4] An efficient test relaxation technique for synchronous sequential circuits
    El-Maleh, A
    Al-Utaibi, K
    [J]. 21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2003, : 179 - 185
  • [5] An efficient test relaxation technique for synchronous sequential circuits
    El-Maleh, A
    Al-Utaibi, K
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (06) : 933 - 940
  • [6] Static test compaction for diagnostic test sets of full-scan circuits
    Pomeranz, I.
    Reddy, S. M.
    [J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2010, 4 (05): : 365 - 373
  • [7] Static test compaction for full-scan circuits based on combinational test sets and nonscan input sequences and a lower bound on the number of tests
    Pomeranz, I
    Reddy, SM
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2004, 53 (12) : 1569 - 1581
  • [8] An efficient test relaxation technique for combinational circuits based on critical path tracing
    El-Maleh, A
    Al-Suwaiyan, A
    [J]. ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 461 - 465
  • [9] Synchronous full-scan for asynchronous handshake circuits
    Beest, FT
    Peeters, A
    Van Berkel, K
    Kerkhoff, H
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (04): : 397 - 406
  • [10] Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing
    Nicolici, N
    Al-Hashimi, BM
    Williams, AC
    [J]. IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2000, 147 (05): : 313 - 322
12345