ATPG for dynamic burn-in test in full-scan circuits

被引：0

作者：

Benso, Alfredo ^{[1
]}

Bosio, Alberto ^{[1
]}

Di Carlo, Stefano ^{[1
]}

Di Natale, Giorgio ^{[1
]}

Prinetto, Paolo ^{[1
]}

机构：

[1] Politecn Torino, Dipartimento Automat & Informat, Corso Duca Abruzzi 24, I-10129 Turin, Italy

来源：

PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Yield and reliability are two key factors affecting costs and profits in the semiconductor industry. Stress testing is a technique based on the application of higher than usual levels of stress to speed up the deterioration of electronic devices and increase yield and reliability. One of the standard industrial approaches-for stress testing is high temperature burn-in. This: work proposes a full-scan circuit ATPG for dynamic burn-in. The goal of the proposed ATPG approach is to generate test patterns able to force transitions into each node of a full scan circuit to guarantee a uniform distribution of the stress during the dynamic burn-in test.

引用

页码：75 / +

页数：2

共 50 条

[1] A Test Pattern Selection Method for Dynamic Burn-in of Logic Circuits Based on ATPG Technique
Yang, Xuan
Cui, Xiaole
Wang, Chao
Lee, Chung-Len
[J]. 2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
[2] Static test compaction for multiple full-scan circuits
Pomeranz, I
Reddy, SM
[J]. 21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS, 2003, : 393 - 396
[3] Static test compaction for diagnostic test sets of full-scan circuits
Pomeranz, I.
Reddy, S. M.
[J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2010, 4 (05): : 365 - 373
[4] An efficient test relaxation technique for combinational & full-scan sequential circuits
El-Maleh, A
Al-Suwaiyan, A
[J]. 20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2002, : 53 - 59
[5] Synchronous full-scan for asynchronous handshake circuits
Beest, FT
Peeters, A
Van Berkel, K
Kerkhoff, H
[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (04): : 397 - 406
[6] Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits
Pomeranz, Irith
Reddy, Sudhakar M.
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (10) : 1907 - 1911
[7] Synchronous Full-Scan for Asynchronous Handshake Circuits
Frank te Beest
Ad Peeters
Kees van Berkel
Hans Kerkhoff
[J]. Journal of Electronic Testing, 2003, 19 : 397 - 406
[8] On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits
Pomeranz, Irith
Reddy, Sudhakar M.
[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (07) : 1135 - 1140
[9] Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences
Pomeranz, I
Reddy, SM
[J]. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2003, : 335 - 340
[10] The accidental detection index as a fault ordering heuristic for full-scan circuits
Pomeranz, I
Reddy, SM
[J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, : 1008 - 1013

← 1 2 3 4 5 →