Combinational test generation for acyclic sequential circuits using a balanced ATPG model

To create a combinational ATPG model for an acyclic sequential circuit, all unbalanced fanouts, i.e., fallouts reconverging with different sequential depths, are moved reward primary inputs using a retiming-like transformation. All flip-flops are then shorted and unbalanced primary input fanouts are split as additional primary inputs. A combinational test vector for a fault in this model is converted into a vector sequence that detects the corresponding fault in the original circuit. An analysis classifies the undetected faults in this model as either untestable or multiply-testable. The latter, typically less than 5% of all faults, are modeled as special single faults in the combinational model. This procedure correctly treats various types of faults, namely, (a) faults detectable by repeating a pattern, (b) faults only detectable by non-repeated patterns, (c) faults only testable as multiple faults in the combinational model, and (d) sequentially undetectable faults. ISCAS '89 benchmark results verify, that the given procedure achieves identical fault coverage and efficiency as a sequential ATPG and uses less CPU time.