Effects of grain boundary width on transfer characteristics of a polysilicon thin-film transistor

The grain boundary scattering effects on carrier transport were studied analytically by considering the grains and grain boundaries that act as the series resistance in the channel of a polycrystalline silicon (poly-Si) thin-film transistor (TFT). Effective carrier mobility (mu*) and drain current (ID) variations were analyzed using the model by changing the grain boundary width (DGB) in the channel as a function of the gate voltage, in the linear region of the poly-Si TFT characteristic at room temperature. mu* and ID were computed for DGB ranging from 1 nm to 10 nm. It was found that for different values of the gate voltage, mu* and ID increased with a decrease in grain boundary width (DGB). A remarkable improvement was observed in device characteristics as DGB was decreased below 2 nm. The predicted results using the present model are in a reasonably good agreement with experimental results, hence confirming the validity of the model.