Fast Substrate Noise Driven Floorplanning for Mixed-Signal Circuits Considering Symmetry Constraints

With the continuous increase of chip complexity and blocks density, the conventional substrate noise optimization tools which are based on some substrate noise models will consume a period of unbearable time. Further more, all the tools only aim at decreasing the total noise but ignore the specific constraints of analog parts such as symmetry constraint. In this paper, we first prove the effectiveness of Block Preference Directed Graph (BPDG) to decrease both noise sum of all analog blocks and noise gradient on symmetrical blocks. Then we implement the concept of BPDG with Corner Block List (CBL), with which the noise estimation process can be finished in linear time. Finally, the experimental results prove that both the time and the quality of final placement can be greatly improved by our method.