A high-throughput pipelined CMA equalizer with minimum latency

被引：0
|
作者：
Mizuno, W [1 ]
Ueda, K [1 ]
Okello, J [1 ]
Ochi, H [1 ]
机构：
[1] Kyushu Inst Technol, Kitakyushu, Fukuoka 804, Japan
来源：
2002 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-IV, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
O42 [声学];
学科分类号：
070206 ; 082403 ;
摘要：
引用
收藏
页码：4184 / 4184
页数：1
相关论文
共 50 条
  • [1] A high-throughput pipelined architecture for blind adaptive equalizer with minimum latency
    Mizuno, M
    Ueda, K
    Okello, J
    Ochi, H
    [J]. 2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2002, : 29 - 32
  • [2] A high throughput pipelined architecture for blind adaptive equalizer with minimum latency
    Mizuno, M
    Okello, J
    Ochi, H
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2003, E86A (08) : 2011 - 2019
  • [3] A high-throughput pipelined architecture for blind adaptive equalization with minimum latency
    Mizuno, M
    Ueda, K
    Okello, J
    Ochi, H
    [J]. THIRTY-SIXTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS - CONFERENCE RECORD, VOLS 1 AND 2, CONFERENCE RECORD, 2002, : 980 - 984
  • [4] High-throughput pipelined mergesort
    Fleming, Kermin
    King, Myron
    Ng, Man Cheuk
    Khan, Asif
    Vijayaraghavan, Muralidaran
    [J]. MEMOCODE'08: SIXTH ACM & IEEE INTERNATIONAL CONFERENCE ON FORMAL METHODS AND MODELS FOR CO-DESIGN, PROCEEDINGS, 2008, : 155 - 158
  • [5] A High-Throughput Pipelined Architecture for JPEG XR Encoding
    Hattori, Koichi
    Tsutsui, Hiroshi
    Ochi, Hiroyuki
    Nakamura, Yukihiro
    [J]. 2009 IEEE/ACM/IFIP 7TH WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA, 2009, : 9 - +
  • [6] High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers
    Lyu, Fei
    Xia, Yan
    Chen, Yuheng
    Wang, Yanxu
    Luo, Yuanyong
    Wang, Yu
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 30 (04) : 544 - 548
  • [7] High-Throughput and Low-Latency Hyperloop
    Eichelberger, Manuel
    Geiter, David T.
    Schmid, Roland
    Wattenhofer, Roger
    [J]. 2020 IEEE 23RD INTERNATIONAL CONFERENCE ON INTELLIGENT TRANSPORTATION SYSTEMS (ITSC), 2020,
  • [8] A high-throughput scalable BNN accelerator with fully pipelined architecture
    Zhe Han
    Jingfei Jiang
    Jinwei Xu
    Peng Zhang
    Xiaoqiang Zhao
    Dong Wen
    Yong Dou
    [J]. CCF Transactions on High Performance Computing, 2021, 3 : 17 - 30
  • [9] A High-Throughput Pipelined Parallel Architecture for JPEG XR Encoding
    Tsutsui, Hiroshi
    Hattori, Koichi
    Ochi, Hiroyuki
    Nakamura, Yukihiro
    [J]. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2012, 11 (04)
  • [10] A high-throughput scalable BNN accelerator with fully pipelined architecture
    Han, Zhe
    Jiang, Jingfei
    Xu, Jinwei
    Zhang, Peng
    Zhao, Xiaoqiang
    Wen, Dong
    Dou, Yong
    [J]. CCF TRANSACTIONS ON HIGH PERFORMANCE COMPUTING, 2021, 3 (01) : 17 - 30
12345