Design of Passive UHF RFID Tag in 130nm CMOS Technology

被引：10

作者：

Hong, Yang ^{[1
]}

Chan, Chi Fat ^{[1
]}

Guo, Jianping ^{[1
]}

Ng, Yuen Sum ^{[1
]}

Shi, Weiwei ^{[1
]}

Leung, Lai Kan ^{[1
]}

Leung, Ka Nang ^{[1
]}

Choy, Chiu Sing ^{[1
]}

Pun, Kong Pang ^{[1
]}

机构：

[1] Chinese Univ Hong Kong, Dept Elect Engn, Shatin, Hong Kong, Peoples R China

来源：

2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 | 2008年

关键词：

D O I：

10.1109/APCCAS.2008.4746284

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a low-power, passive, UHF RFID tag design compatible with EPC (TM) C1G2 protocol. In order to reduce its cost, diode-connected NMOS in a standard CMOS technology is used instead of Schottky diodes. With the help of low-threshold-voltage, triple-well NMOS, a minimum input power of -7.6dBm is achieved. A sub-1V, low temperature-coefficient voltage reference using self-biased mutual compensation is proposed without large resistors to save the chip area. In addition, an energy-aware irregular clock structure, together with clock gating, achieves low power consumption in the baseband processor. The whole tag is implemented in a 130nm CMOS technology and the total chip area is 1200umx1220um.

引用

页码：1371 / 1374

页数：4

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