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- [2] BIST-Guided ATPG 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, : 244 - 249
- [3] Test cost minimization for hybrid BIST IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2000, : 283 - 291
- [4] BIST vs. ATE: Need a different vehicle? INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 1148 - 1148
- [5] Balancing Test Cost Reduction vs. Measurements Accuracy at Test Time 2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2015,
- [6] ATPG versus logic BIST - Now and in the future INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, : 1181 - 1181
- [7] Scan-based ATPG or logic BIST? INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, : 1183 - 1183
- [8] BIST vs. ATE for testing system-on-a-chip INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS, 1998, : 1147 - 1147
- [9] Special ATPG to correlate test patterns for low-overhead mixed-mode BIST SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS, 1998, : 492 - 499
- [10] Comparison of various ATPG techniques to determine Optimal BIST 2ND INTERNATIONAL CONFERENCE ON INTELLIGENT CIRCUITS AND SYSTEMS (ICICS 2018), 2018, : 93 - 98