Design of low-power low-area asynchronous iterative multiplier

被引：2
|
作者：
You, Heng [1 ,2 ]
Hei, Yong [1 ]
Yuan, Jia [1 ]
Tang, Weidi [3 ]
Bai, Xu [1 ,2 ]
Qiao, Shushan [1 ,2 ]
机构：
[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China
[2] Univ Chinese Acad Sci, Beijing 100049, Peoples R China
[3] Univ Sci & Technol China, Shushan 230027, Anhui, Peoples R China
来源：
IEICE ELECTRONICS EXPRESS | 2019年 / 16卷 / 11期
基金：
中国国家自然科学基金;
关键词：
low-power; low-area; iterative multiplier; asynchronous circuits; useless switching reduction; ENERGY;
D O I：
10.1587/elex.16.20190212
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a 16 times 16 low-power low-area asynchronous iterative multiplier is proposed. The multiplier diminishes 2 bits at a time with an iterative structure, to filter out the useless switching activities, we employ a finishing detector to dynamically detect the end of the computation and stop iteration ahead of schedule. Additionally, with the employment of finishing detectors, the proposed multiplier could provide a much faster average speed than synchronous approach. Post-layout simulation results show that the asynchronous multiplier offers up to 74% power reduction compared with the synchronous design. Simultaneously, the proposed design also exhibits a prominent area reduction compared with other non-iterative multiplier benefited from the iterative architecture.
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收藏
页数：5
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