The "quiet" state - A new approach to low-power multiplier design

被引：0

作者：

Mallios, N ^{[1
]}

Burgess, N ^{[1
]}

机构：

[1] Cardiff Sch Engn, Cardiff CF24 0YF, S Glam, Wales

来源：

CONFERENCE RECORD OF THE THIRTY-SEVENTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2 | 2003年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper proposes a novel implementation of the (4:2) redundant adder, which takes advantage of a "don't care" state to introduce a "quiet" state that suppresses glitch propagation in a multiplier's reduction tree. Simulations show that using two 32-bit random words, without Booth encoding, as much as a 10% reduction in driven capacitance can be achieved, which could translate to larger power savings due to the smaller switching activity at the adder's output wires.

引用

页码：2222 / 2226

页数：5

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