Jitter tolerance calibration for high-speed serial interfaces

被引：1

作者：

Tsimpos, A. ^{[1
]}

Demartinos, A. C. ^{[1
]}

Vlassis, S. ^{[1
]}

Souliotis, G. ^{[2
]}

机构：

[1] Univ Patras, Dept Phys, Elect Lab, Patras 26504, Greece

[2] Technol Educ Inst Western Greece, Dept Elect Engn, Patras 26334, Greece

来源：

INTEGRATION-THE VLSI JOURNAL | 2017年 / 57卷

关键词：

High-speed serial interfaces; Jitter tolerance simulation; verilog-AMS; M-PHY standard; CLOCK;

D O I：

10.1016/j.vlsi.2016.12.008

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A jitter tolerance calibration test bench suitable for high speed serial interfaces (HSSI) using verilog-AMS is proposed in this paper. The jitter tolerance simulation environment can be easily parameterized in order to be compliant to any HSSI standard specification. As an example, the proposed solution is applied for the jitter tolerance simulation and characterization of the most updated M-PHY ver.3 HSSI standard for mobile applications. A comprehensive method for the calculation of the jitter noise frequency ingredients and the calibration of jitter noise sources is also proposed resulting a jitter tolerance mask compliant with the M-PHY ver.3 specifications. Using the proposed implementation the transistor level and behavioral modules co-simulation time could be significantly minimized.

引用

页码：101 / 107

页数：7

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